It is known that the design of processor systems involves a tradeoff between performance and power dissipation. In particular, processor design can involve efforts to maximize performance while limiting the power dissipated by the processor. This tradeoff can be particularly important when designing processors for use in mobile applications (such as laptop computers), where power may be provided by a battery having very limited capacity.
Processors typically include on-chip cache memories that can significantly increase the performance of the processor. The inclusion of on-chip cache memories also can increase the power dissipated by the processor for at least three reasons. One of the reasons that on-chip cache memories increase processor power dissipation, is that on chip cache memories are typically implemented as static random access memories to provide fast access to the tag and data information stored therein. As is well known to those skilled in the art, static random access memories can dissipate significantly greater power than equivalent dynamic random access memories. Another reason that on-chip cache memories increase processor power dissipation is that the transistors which make up the on-chip cache memory can be spaced closely together thereby increasing the amount of power per unit area that is dissipated by the processor. Still another reason that on-chip cache memories increase processor power dissipation is that on-chip cache memories can be frequently accessed (for example, during the processor's instruction cycle).
A number of approaches have been used in attempts to reduce the power dissipation associated with on-chip cache memories. For example, some systems have employed the use of multiple line buffers to reduce the power dissipated by processor cache memory. Such approaches are discussed, for example, in Reducing Power In Super scalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit-Line Segmentation by Ghose et al., Department of Computer Science, State University of New York, Binghamton, N.Y. 13902-6000 ACM1-58113-133-X/99/0008, the disclosure of which is included herein by reference.
Other approaches have employed the use of filter caches to reduce power dissipation in processor cache memory. Such approaches are discuss, for example, in The Filter Cache: An Energy Efficient Memory Structure by Kin et al., The Department of Electrical Engineering, UCLA Electrical Engineering, 1997, IEEE 1072-4451/97, the disclosure of which is included herein by reference.
Other approaches have focused on cache memories that operate in a high speed mode and a low speed mode. Such approaches are discussed, for example, in U.S. Pat. No. 5,920,888 to Shirotiro et al., the disclosure of which is included herein by reference.
It is also known to use what is commonly referred to as “dynamic frequency scaling” to change the clock provided to the cache memory, so that the cache memory operates in a low frequency/low power mode to reduce the power dissipated by the cache memory when in the low frequency mode.